The selected candidate will have the following responsibilities:
- Top/Block level RTL (Verilog or System Verilog) design, integration.
- Use of various design tools (Linting, CDC, LEC, Fishtail, CLP etc.) to check and improve design quality
- Implementation of Low power logic, targeting power, performance, area, and timing goals.
- Work with 3rd party physical design team on all aspects of synthesis, timing analysis, support physical layout, Linting, CDC, LEC tools to implement design and check design quality
- Work with Design Verification team on top-level or block level functional/gate level verification and code coverage, including power aware debug.
- Bachelor’s degree in Engineering, Science or closely related field
- 8+ years of RTL design experience
- 5+ years of experience with relevant ASIC Design technologies
- Bachelor’s degree in Electrical or Computer Engineering.
- Knowledge of C/C++, Matlab/Simulink DSP conversion, general DSP design for digital applications
- ASIC design and verification experiences including architecture, RTL design in Verilog/system Verilog.
- Experience with design databases. Experience with synthesis, and timing closure. Experience with scripting tools (Perl/Python) Experience with DC, LINT, LEC, and CDC.
- Experience working with remote design centers, and outsourced design resources
- Familiarity with Synopsys Synthesis Tools Design Compiler, VCS, DFT Compiler, Formality, Prime Power, Verdi-3)
- Familiarity with AXI/AHB bus protocols and SoC integration experiences
- Familiarity with MBIST and DFT flow
- Experience with ARM IP for ASIC (Cortex M55 ,A53, Corstone -700 or -500 )
- Excellent communication, interpersonal and teamwork skills
- Efficient skills in debugging and root causing design issues
- FPGA experience is a plus
- Gate level Simulation debug and usage of power extraction tools a plus